1. Field of the Invention
The present invention relates to a display system, and more particularly, to a frame rate conversion apparatus and method.
2. Description of the Related Art
In general, a display system, such as a liquid crystal display (LCD) monitor, displays an image at a vertical frequency or frame rate of 60±5 KHz. Since image signals are input at various frame rates, the display system converts the frames of the image signals into frame rates that are permitted by a particular display device, such as an LCD panel. The display system performs frame rate down conversion on the input image signal when the frame rate of an input image signal is greater than permitted in the display device, and performs frame rate up conversion otherwise. Unlike a signal output by a video player or a TV signal, the frame rate of a signal output by a graphic card of a computer is likely to be greater than the frame rate required by the display device such as an LCD panel. Thus, the display system requires an apparatus that performs frame rate down conversion. Since advancement in technologies increases the frame rate permitted in the display device such as the LCD panel, the need for frame rate conversion continues to become reduced. Nonetheless, frame rate conversion is still required to display signals with various frame rates on a display device.
FIG. 1 is a block diagram of a conventional LCD system 100 with a frame rate conversion function. The LCD system 100 includes a frame rate conversion unit 110, a synchronization detector 120, an external memory 130, an LCD driving circuit unit 140, and an LCD panel 150. When a three color signal, i.e., R (Red), G (Green), and B (Blue) image data, and a synchronization signal output from an external device such as a graphic device are input to the LCD system 100, the frame rate conversion unit 110 converts the frame rates of the R, G, B data using the external memory 130. When the converted R, G, B data is input to the LCD driving circuit unit 140, the LCD driving circuit unit 140 processes the converted R, G, B data to be displayed on the LCD panel 150.
FIG. 2 is a detailed block diagram of the frame rate conversion unit 110 of FIG. 1. Referring to FIG. 2, the frame rate conversion unit 110 includes a First In First Out (FIFO) memory 111, a second FIFO memory 112, and a controller 113. When the R, G, B data output from the external device is sequentially input to the first FIFO memory 111, the external memory 130, and the second FIFO memory 112, the frame rate of the R, G, B data is converted into a frame rate required by the LCD panel 150 and the converted R, G, B data is input to the LCD driving circuit unit 140. The controller 113 controls input of data to and output of data from the first FIFO memory 111, the external memory 130, and the second FIFO memory 112, using an input vertical synchronization signal VS and an input horizontal synchronization signal HS detected by the synchronization detector 120. The controller 113 also generates an output vertical synchronization signal OVS, an output horizontal synchronization signal OHS, and an output data enable signal ODE whose frame rates are sufficient to drive the LCD panel 150, and outputs them to the LCD driving circuit unit 140.
As described above, since the frequencies of the output synchronization signals OVS and OHS are different from those of the synchronization signals VS and HS input from an external device. The frame rate of image data input outside the LCD system 100 has been converted. In this case, only when the output data enable signal ODE is at a logic high level, the LCD driving circuit unit 140 outputs the image data to the LCD panel 150 so that the image data is displayed on the LCD panel 150.
FIG. 3 illustrates the relationship among the input synchronization signals VS and HS and vertical and horizontal data enable signals VDE and HDE. Referring to FIG. 3, an image is displayed on the LCD panel 150 when both the vertical data enable signal VDE and the horizontal data enable signal HDE are at a logic high level. The period of the vertical data enable signal VDE is shorter than that of the vertical synchronization signal VS, and the period of the horizontal data enable signal HDE is shorter than that of the horizontal synchronization signal HS. In other words, an output data enable signal DE shown in FIG. 4 goes high when both the vertical data enable signal VDE and the horizontal data enable signal HDE are at a logic high, and an image is displayed on the LCD panel 150 when the LCD driving circuit unit 140 operates in response to the high-level output data enable signal DE. FIG. 4 is a timing diagram illustrating the relationship among the vertical synchronization signals VS and OVS and the data enable signals DE and ODE generated before and after frame rate down conversion is performed. Referring to FIG. 4, the period of the output vertical synchronization signal OVS is longer than that of the input vertical synchronization signal VS. Thus, frame rate down conversion must be performed by decimating or interpolating parts of the frames of input signals to control the frame rates of output signals. For instance, when the frequency of an input frame is 75 Hz and the frequency of an output frame is 60 Hz, one of every five frames must be rejected as shown in FIG. 5.
As described above, conventional frame rate conversion requires the external memory 130, and the FIFO memories 111 and 112 and the controller 113 to drive the external memory 130. Accordingly, an LCD system 100 with a frame rate conversion function has a complicated circuit construction and is expensive to manufacture. Such problems also occur in a low-price display system that performs only frame rate down conversion to realize a Picture-In-Picture (PIP) function; and a multi-sync system that performs frame rate down/up conversion on signals with various frame rates, e.g., a signal output from a graphic card of a computer, a signal output from a video player, and a TV signal, and displays these signals. For instance, in order to display a PIP screen with a frame rate of 60 Hz in a screen with a frame rate of 75 Hz, the frame rate of a part of the screen with the frame rate of 75 Hz may be converted down to the frame rate of 60 Hz.